It is known to reduce the increase of power consumption of a large-scale semiconductor integrated circuit (LSI) using static timing analysis (STA) or the like by the simulation program with integrated circuit emphasis (SPICE) or the like upon designing of the LSI (for example, refer to Patent Documents 1 to 3). In an example, an optimum power supply voltage value is determined for each device by incorporating a ring oscillator in the LSI and using a table indicating a relationship between an oscillation period of the incorporated ring oscillator and the optimum voltage value of the LSI. When the table indicating a relationship between an oscillation period and an optimum voltage value is created, the dispersion of process parameters such as the gate length is reflected on the table by analysis of a critical path by a simulation of the SPICE or the like. By determining an optimum voltage value using the table on which the dispersion of a plurality of process parameters such as the gate length is reflected, the optimum voltage value is determined with a higher degree of accuracy than a conventional model by which it is estimated that all process parameters vary all at once in the worst direction. Since the table indicating a relationship between an oscillation period and an optimum voltage value is created for each logic circuit in which a critical path is different from that in the other logic circuits, static timing analysis by a simulation of the SPICE or the like is executed for each logic circuit in which a critical path is different from that of the other logic circuits. Since a simulation of the SPICE or the like is executed generally with a great number of processing steps, there is the possibility that the load on a circuit designer increases by executing static timing analysis by a simulation of the SPICE or the like for each logic circuit in which a critical path is different from that of the other logic circuits.
Further, a programmable logic device (PLD) that is also called field programmable gate array (FPGA) and is a logic circuit capable of being reconfigured in accordance with a change of a circuit to be incorporated is known (for example, refer to Patent Documents 4 and 5). The FPGA includes a great number of basic logic cell circuits and a coupling switch circuit that couples the basic logic cell circuits with each other. The basic logic cell circuits are individually configured so as to perform a desired operation and are coupled with each other through the coupling switch circuit.
As examples of the prior art, Japanese Laid-open Patent Publication No. 2009-86848, Japanese Laid-open Patent Publication No. 2012-203561, Japanese National Publication of International Patent Application No. 2011-530763, Japanese Laid-open Patent Publication No. 2006-163815 and Japanese Laid-open Patent Publication No. 2008-263261 are known.